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this is information on a product in full production. june 2014 docid14493 rev 8 1/25 L6390 high voltage high/low-side driver datasheet - production data features ? high voltage rail up to 600 v ? dv/dt immunity 50 v/nsec in full temperature range ? driver current capability: 290 ma source, 430 ma sink ? switching times 75/35 nsec rise/fall with 1 nf load ? 3.3 v, 5 v ttl/cmos inputs with hysteresis ? integrated bootstrap diode ? operational amplifier for advanced current sensing ? comparator for fast fault protection ? smart shutdown function ? adjustable deadtime ? interlocking function ? compact and simplified layout ? bill of material reduction applications ? home appliances ? motor drivers ? dc, ac, pmdc and pmac motors ? foc and sensorless bemf detection systems ? industrial applications and drives ? induction heating ? hvac ? factory automation ? power supply systems description the L6390 is a full featured high voltage device manufactured with the bcd? ?offline? technology. it is a single-chip half-bridge gate driver for n-channel power mosfets or igbts. the high-side (floating) se ction is able to work with voltage rail up to 600 v. both device outputs can sink and source 430 ma and 290 ma respectively. prevention from cross conduction is ensured by interlocking and programmable deadtime functions. the device has dedicated input pins for each output and a shutdown pin. the logic inputs are cmos/ttl compatible do wn to 3.3 v for easy interfacing with control devices. matched delays between low-side and high-side sections guarantee no cycle distortion and allow high frequency operation. the L6390 embeds an operational amplifier suitable for advanced current sensing in applications such as field oriented motor control or for sensorless bemf detection. a comparator featuring advanced smartsd function is also integrated in the device, ensuring fast and effective protection against fault events like overcurrent, overtemperature, etc. the L6390 device features also uvlo protection on both the lower and upper driving sections, preventing the power switches from operating in low efficiency or dangerous conditions. the integrated bootstrap diode as well as all of the integrated features of this ic make the application pcb design easier, more compact and simple thus reducing the overall bill of material. the device is available in a dip-16 tube and so-16 tube, and tape and reel packaging options. dip-16 so-16 www.st.com
contents L6390 2/25 docid14493 rev 8 contents 1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 4 electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 4.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 4.2 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 4.3 recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 5 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 5.1 ac operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 5.2 dc operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 6 waveforms definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 7 smart shutdown function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 8 typical application diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 9 bootstrap driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 c boot selection and charging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 10 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 11 order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 12 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
docid14493 rev 8 3/25 L6390 block diagram 25 1 block diagram figure 1. block diagram uv detection level shifter bootstrap driver s v cc lvg driver hin lin hvg driver hvg boot out lvg uv detection op+ op- gnd opout sd/od dt opamp dead time r logic shoot through prevention sd latc h floating structure comparator + v ref cp+ 1 2 11 14 15 16 7 5 8 3 4 10 9 6 smart sd from lvg vcc vcc 5v + - + - 5v
pin connection L6390 4/25 docid14493 rev 8 2 pin connection figure 2. pin connection (top view) table 1. pin description pin n # pin name type function 1lin i low-side driver logic input (active low) 2sd /od (1) 1. the circuit provides less than 1 v on the lvg and hvg pins (at isink = 10 ma), with v cc > 3 v. this allows the omission of the ?bleeder? resistor connected betw een the gate and the source of the external mosfet normally used to hold the pin low; the gate driv er assures low impedance also in sd condition. i/o shutdown logic input (active low)/open drain (comparator output) 3 hin i high-side driver logic input (active high) 4 vcc p lower section supply voltage 5 dt i deadtime setting 6 op- i op amp inverting input 7 opout o op amp output 8 gnd p ground 9 op+ i op amp non-inverting input 10 cp+ i comparator input 11 lvg (1) o low-side driver output 12, 13 nc not connected 14 out p high-side (floating) common voltage 15 hvg (1) o high-side driver output 16 boot p bootstrap supply voltage hin sd/od lin vcc 1 3 2 4nc out hvg boo t 16 15 14 13 opout op- dt cp+ lvg nc 12 11 10 9 5 7 6 8 op+ gnd
docid14493 rev 8 5/25 L6390 truth table 25 3 truth table table 2. truth table input output sd lin hin lvg hvg lx (1) 1. x: don't care. x (1) ll hhl l l hlhll hllhl hhhlh
electrical data L6390 6/25 docid14493 rev 8 4 electrical data 4.1 absolute maximum ratings 4.2 thermal data table 3. absolute maximum ratings symbol parameter value unit min. max. v cc supply voltage - 0.3 21 v v out output voltage v boot - 21 v boot + 0.3 v v boot bootstrap voltage - 0.3 620 v v hvg high-side gate output voltage v out - 0.3 v boot + 0.3 v v lvg low-side gate output voltage - 0.3 v cc + 0.3 v v op+ op amp non-inverting input - 0.3 v cc + 0.3 v v op- op amp inverting input - 0.3 v cc + 0.3 v v cp+ comparator input voltage - 0.3 v cc + 0.3 v v i logic input voltage - 0.3 15 v v od open drain voltage - 0.3 15 v dv out /dt allowed output slew rate 50 v/ns p tot total power dissipation (t a = 25 c) 800 mw t j junction temperature 150 c t stg storage temperature -50 150 c table 4. thermal data symbol parameter so-16 dip-16 unit r th(ja) thermal resistance junction to ambient 155 100 c/w
docid14493 rev 8 7/25 L6390 electrical data 25 4.3 recommended operating conditions table 5. recommended operating conditions symbol pin parameter test condition min. max. unit v cc 4 supply voltage 12.5 20 v v bo (1) 1. v bo = v boot - v out . 16 - 14 floating supply voltage 12.4 20 v v out 14 dc output voltage - 9 (2) 2. lvg off. v cc = 12.5 v. logic is operational if v boot > 5 v. refer to the an2738 for more details. 580 v f sw switching frequency hvg, lvg load c l = 1 nf 800 khz t j junction temperature -40 125 c
electrical characteristics L6390 8/25 docid14493 rev 8 5 electrical characteristics 5.1 ac operation table 6. ac operation el ectrical characteristics (v cc = 15 v; t j = +25 c) symbol pin parameter test condition min. typ. max. unit t on 1 vs. 11 3 vs. 15 high/low-side driver turn-on propagation delay v out = 0 v v boot = v cc c l = 1 nf v i = 0 to 3.3 v see figure 3. 50 125 200 ns t off high/low-side driver turn-off propagation delay 50 125 200 ns t sd 2 vs. 11, 15 shutdown to high/low-side driver propagation delay 50 125 200 ns t isd comparator triggering to high/low-side driver turn-off propagation delay measured applying a voltage step from 0 v to 3.3 v to pin cp+. 50 200 250 ns mt delay matching, hs and ls turn-on/off 30 ns dt 5 deadtime setting range (1) r dt = 0, c l = 1 nf 0.1 0.18 0.25 ? s r dt = 37 k ? , c l = 1 nf, c dt = 100 nf 0.48 0.6 0.72 ? s r dt = 136 k ? , c l = 1 nf, c dt = 100 nf 1.35 1.6 1.85 ? s r dt = 260 k ? , c l = 1 nf, c dt = 100 nf 2.6 3.0 3.4 ? s mdt matching deadtime (2) r dt = 0, c l = 1 nf 80 ns r dt = 37 k ? , c l = 1 nf, c dt = 100 nf 120 ns r dt = 136 k ? , c l = 1 nf, c dt = 100 nf 250 ns r dt = 260 k ? , c l = 1 nf, c dt = 100 nf 400 ns ? t r 11, 15 rise time c l = 1 nf 75 120 ns t f fall time c l = 1 nf 35 70 ns 1. see figure 4 . 2. mdt = | dt lh - dt hl | see figure 5 on page 13 .
docid14493 rev 8 9/25 L6390 electrical characteristics 25 figure 3. timing figure 4. typical deadtime vs. dt resistor value hin hvg 50% 10% 90% 50% tr tf ton toff 90% 10% lin lvg 50% 10% 90% 50% tr tf ton toff 90% 10% lvg/h vg sd 90% 50% tf tsd 10% 5gwn2kp '7xv ? $ssur[lpdwhgirupxodiru 5gwfdofxodwlrqw\s 5gw>n @ '7>?v@
electrical characteristics L6390 10/25 docid14493 rev 8 5.2 dc operation table 7. dc operation elect rical characteristics (v cc = 15 v; t j = + 25 c) symbol pin parameter test condition min. typ. max. unit low supply voltage section v cc_hys 4 v cc uv hysteresis 1200 1500 1800 mv v cc_thon v cc uv turn-on threshold 11.5 12 12.5 v v cc_thoff v cc uv turn-off threshold 10 10.5 11 v i qccu undervoltage quiescent supply current v cc = 10 v sd = 5 v; lin = 5 v; hin = gnd; r dt = 0 ? ; cp+ = op+ = gnd; op- = 5 v 90 120 150 ? a i qcc quiescent current v cc = 15 v sd = 5 v; lin = 5 v; hin = gnd; r dt = 0 ? ; cp+ = op+ = gnd; op- = 5 v 300 720 1000 ? a v ref internal reference voltage 500 540 580 mv bootstrapped supply voltage section (1) v bo_hys 16 v bo uv hysteresis 1200 1500 1800 mv v bo_thon v bo uv turn-on threshold 11.1 11.5 12.1 v v bo_thoff v bo uv turn-off threshold 9.8 10 10.6 v i qbou undervoltage v bo quiescent current v bo = 9 v sd = 5 v; lin and hin = 5 v; r dt = 0 ? ; cp+ = op+ = gnd; op- = 5 v 30 70 110 ? a i qbo v bo quiescent current v bo = 15 v sd = 5 v; lin and hin = 5 v; r dt = 0 ? ; cp+ = op+ = gnd; op- = 5 v 30 150 240 ? a i lk high voltage leakage current v hvg = v out = v boot = 600 v 10 ? a r ds(on) bootstrap driver on- resistance (2) lvg on 120 ?
docid14493 rev 8 11/25 L6390 electrical characteristics 25 driving buffers section i so 11, 15 high/low-side source short- circuit current v in = v ih (t p < 10 ? s) 200 290 ma i si high/low-side sink short- circuit current v in = v il (t p < 10 ? s) 250 430 ma logic inputs v il 1, 2, 3 low level logic threshold voltage 0.8 1.1 v v ih high level logic threshold voltage 1.9 2.25 v v il_s 1, 3 single input voltage lin and hin connected together and floating 0.8 v i hinh 3 hin logic ?1? input bias current hin = 15 v 110 175 260 ? a i hinl hin logic ?0? input bias current hin = 0 v 1 ? a i linl 1 lin logic ?0? input bias current lin = 0 v 3 6 20 ? a i linh lin logic ?1? input bias current lin = 15 v 1 ? a i sdh 2 sd logic ?1? input bias current sd = 15 v 10 40 100 ? a i sdl sd logic ?0? input bias current sd = 0 v 1 ? a 1. v bo = v boot - v out . 2. r dson is tested in the following way: r dson = [(v cc - v cboot1 ) - (v cc - v cboot2 )] / [i 1 (v cc ,v cboot1 ) - i 2 (v cc ,v cboot2 )] where i 1 is the pin 16 current when v cboot = v cboot1 , i 2 when v cboot = v cboot2 . table 7. dc operation electrical characteristics (v cc = 15 v; t j = + 25 c) (continued) symbol pin parameter test condition min. typ. max. unit
electrical characteristics L6390 12/25 docid14493 rev 8 table 8. op amp characteristics (1) (v cc = 15 v, t j = +25 c) symbol pin parameter test condition min. typ. max. unit v io 6, 9 input offset voltage v ic = 0 v, v o = 7.5 v 6 mv i io input offset current v ic = 0 v, v o = 7.5 v 440na i ib input bias current (2) 100 200 na v icm input common mode voltage range 0v cc -4 v v opout 7 output voltage swing opout = op-; no load 0.07 v cc -4 v i o output short-circuit current source, v id = +1; v o = 0 v 16 30 ma sink,v id = -1; v o = v cc 50 80 ma sr slew rate v i = 1 ? 4 v; c l = 100 pf; unity gain 2.5 3.8 v/ ? s gbwp gain bandwidth product v o = 7.5 v 8 12 mhz a vd large signal voltage gain r l = 2 k ? 70 85 db svr supply voltage rejection ratio vs. v cc 60 75 db cmrr common mode rejection ratio 55 70 db 1. the operational amplifier is disabled when v cc is in uvlo condition. 2. the direction of the input current is out of the ic. table 9. sense comparator characteristics (1) (v cc = 15 v, t j = +25 c) symbol pin parameter test condition min. typ. max. unit i ib 10 input bias current v cp+ = 1 v 1 ? a v ol 2 open drain low level output voltage i od = - 3 ma 0.5 v t d_comp comparator delay sd /od pulled to 5 v through 100 k ? resistor 90 130 ns sr 2 slew rate c l = 180 pf; r pu = 5 k ? 60 v/ ? s 1. the comparator is disabled when v cc is in uvlo condition.
docid14493 rev 8 13/25 L6390 waveforms definition 25 6 waveforms definition figure 5. deadtime and inte rlocking waveforms definition lin hin lvg hvg lin hin lvg hvg lin hin lvg hvg lin hin lvg hvg dt lh dt hl dt lh dt hl dt lh dt hl dt lh dt hl gate driver outputs off (half-bridge tri-state) interlocking interlocking g in g in control signal edges overlapped: interlocking + dead time control signals edges synchronous (*): dead time control signals edges not overlapped, but inside the dead time: dead time control signals edges not overlapped, outside the dead time: direct driving (*) hin and lin can be connected togheter and driven by just one control signal interlocking interlocking g i g in gate driver outputs off (half-bridge tri-state) gate driver outputs off (half-bridge tri-state) gate driver outputs off (half-bridge tri-state) gate driver outputs off (half-bridge tri-state) gate driver outputs off (half-bridge tri-state) gate driver outputs off (half-bridge tri-state) gate driver outputs off (half-bridge tri-state)
smart shutdown function L6390 14/25 docid14493 rev 8 7 smart shutdown function the L6390 device integrates a comparator committed to the fault sensing function. the comparator has an internal voltage reference v ref connected to the inve rting input, while the non-inverting input is available on the pin 10. the comparator input can be connected to an external shunt resistor in order to implement a simple overcurrent detection function. the output signal of the comparator is fed to an integrated mosfet with the open drain output available on the pin 2, shared with the sd input. when the comparator triggers, the device is set in shutdown state and both its outputs are set to low level leaving the half-bridge in tristate. figure 6. smart shutdown timing waveforms sd/od from/to controller v bias c sd r sd smart sd logic r on_od shut down circuit r pd_sd an approximation of the disable time is given by: where: hin/lin hvg/lvg open drain gate (internal) comp vref cp+ protection fast shut down : the driver outputs are set in sd state immediately after the comparator triggering even if the sd signal has not yet reach the lower input threshold disable time sd/od am12947v1
docid14493 rev 8 15/25 L6390 smart shutdown function 25 in common overcurrent protection architectures the comparator output is usually connected to the sd input and an rc network is connec ted to this sd/od line in order to provide a monostable circuit, which implements a protec tion time that follows the fault condition. differently from the common fault detecti on systems, the L6390 smart shutdown architecture allows immediate turn-off of the outputs of the gate driver in the case of fault, by minimizing the propagation delay between the fault detection event and the actual output switch-off. in fact, the time de lay between the fault detection and the output turn-off is no longer dependent on the value of the external rc network connected to the sd/od pin. in the smart shutdown circuitry the fault signal has a preferential path which directly switches off the outputs after the comparator triggering. at the same time the internal logic turns on the open drain output and holds it on until the sd voltage goes below the sd logic input lower threshold. when such threshold is re ached, the open drain output is turned off, allowing the external pull-up to recharge the capacitor. the driver outputs restart following the input pins as soon as the voltage at the sd/od pin reaches the higher threshold of the sd logic input. the smart shutdown system pr ovides the possibility to increase the time constant of the external rc network (that deter mines the disable time after the fault event) up to very large values without increasing the delay time of the protection. any external signal provided to the sd pin is not latched and can be used as control signal in order to perform, for instance, pwm chopping through this pin. in fact when a pwm signal is applied to the sd input and the logic input s of the gate driver are stable, the outputs switch from the low level to the state defined by the logic inputs and vice versa. in some applications it may be useful to latch the driver in the shutdown condition for an arbitrary time, until the controller decides to reset it to normal operation. this may, for example, be achieved with a circuit similar to the one shown in figure 7 . when the open drain starts pulling down the sd/od pin, the ex ternal latch turns on and keeps the pin to gnd, preventing it from being pulled up agai n once the sd logic input lower threshold is reached and the internal open drain turns off. one pin of the controller is used to release the external latch, and one to externally force a shutdown condition and also to read the status of the sd/od pin. figure 7. protection latching example circuit in applications using only one L6390 for the pr otection of several different legs (such as a single-shunt inverter, for example) it may be useful to implement the resistor divider shown in figure 8 . this simple network allows the pushing of the sd pins of the other devices to a voltage lower than L6390 v il , so that each device can reach its low logic level regardless of part-to-part variations of the thresholds. sd_reset sd_force/sense gnd vdd c 3.3 / 5 v 3.3 / 5 v r1 r2 r3 r4 hvg out lvg vboot op+ op- opout dt cp+ L6390 sd/od gnd vcc hin lin + + - vcc to other driver/devices am12949v1 20 k 1.5 k 2.2 k 20 k
smart shutdown function L6390 16/25 docid14493 rev 8 figure 8. sd level shifting example circuit sd_sense sd_force gnd vdd c vdd vcc r1 9*r r3 2*r hvg out lvg vboot op+ op- opout dt cp+ L6390 sd/od gnd vcc hin lin + + - vcc hv bus l639x l639x sd/od sd/od c2 c3 c1 c2, c3: small noise filtering capacitors c1: disable time setting capacitor r2 r am12948v1
docid14493 rev 8 17/25 L6390 typical application diagram 25 8 typical application diagram figure 9. application diagram uv detection level shifter bootstrap driver s v cc lvg driver v cc hin lin hvg driver hvg boot h.v. to load out lvg cboot uv detection + - op+ op- gnd opout sd/od dt opamp dead time r logic shoot through prevention floating structure + - comparator + v ref cp+ sd latch 5v 1 2 11 14 15 16 7 5 8 3 4 10 9 6 smart sd from lvg + from controller from controller from/to controller to adc v bias v bias vcc vcc 5v
bootstrap driver L6390 18/25 docid14493 rev 8 9 bootstrap driver a bootstrap circuitry is needed to supply the high voltage section. this function is normally accomplished by a high voltage fast recovery diode ( figure 10 .a). in the L6390 device a patented integrated structure replaces the exte rnal diode. it is realized by a high voltage dmos, driven synchronously with the low-side driver (lvg), with a diode in series, as shown in figure 10 .b. an internal charge pump ( figure 10 .b) provides the dmos driving voltage. c boot selection and charging to choose the proper c boot value the external mos can be seen as an equivalent capacitor. this capacitor c ext is related to the mos total gate charge: equation 1 the ratio between the capacitors c ext and c boot is proportional to the cyclical voltage loss. it must be: equation 2 c boot >>> c ext e.g.: if q gate is 30 nc and v gate is 10 v, c ext is 3 nf. with c boot = 100 nf the drop would be 300 mv. if hvg must be supplied for a long time, the c boot selection must also take the leakage and quiescent losses into account. e.g.: hvg steady-state consumption is lower than 240 ? a, so if hvg t on is 5 ms, c boot must supply 1.2 ? c to c ext . this charge on a 1 ? f capacitor means a voltage drop of 1.2 v. the internal bootstrap driver offers important advantages: the external fast recovery diode can be avoided (it usually has a high leakage current). this structure can work only if v out is close to gnd (or lower) and, at the same time, the lvg is on. the charging time (t charge ) of the c boot is the time in whic h both conditions are fulfilled and it must be long enough to charge the capacitor. the bootstrap driver introduces a voltage drop due to the dmos r dson (typical value: 120 ? ). this drop can be neglected at low switching frequency, but it should be taken into account when operating at high switching frequency. c ext q gate v gate ------------- - =
docid14493 rev 8 19/25 L6390 bootstrap driver 25 the following equation is useful to compute the drop on the bootstrap dmos: equation 3 where q gate is the gate charge of the external power mosfet, r dson is the on-resistance of the bootstrap dmos and t charge is the charging time of the bootstrap capacitor. for example: using a power mosfet with a total gate charge of 30 nc, the drop on the bootstrap dmos is about 1 v, if the t charge is 5 ? s. in fact: equation 4 v drop should be taken into account when the voltage drop on c boot is calculated: if this drop is too high, or the circuit topology doesn?t allo w a sufficient charging time, an external diode can be used. figure 10. bootstrap driver v drop i ch e arg r dson v drop ? q gate t ch e arg ------------------ r dson == v drop 30nc 5 ? s -------------- - 120 ? 0.7v ? ? = to load d99in1067 h.v. hvg ab lvg hvg lvg c boot to load h.v. c boot d boot boot v cc v cc out out boot
package information L6390 20/25 docid14493 rev 8 10 package information in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack specifications, grade definitions a nd product status are available at: www.st.com . ecopack is an st trademark. figure 11. dip-16 package outline table 10. dip-16 package mechanical data symbol dimensions (mm) min. typ. max. a1 0.51 b 0.77 1.65 b 0.5 b1 0.25 d 20 e 8.5 e 2.54 e3 17.78 f 7.1 i 5.1 l 3.3 z 1.27 3&
docid14493 rev 8 21/25 L6390 package information 25 figure 12. so-16 narrow package outline table 11. so-16 narrow package mechanical data symbol dimensions (mm) min. typ. max. a 1.75 a1 0.10 0.25 a2 1.25 b 0.31 0.51 c 0.17 0.25 d 9.80 9.90 10.00 e 5.80 6.00 6.20 e1 3.80 3.90 4.00 e1.27 h 0.25 0.50 l 0.40 1.27 k0 8 ccc 0.10 '
package information L6390 22/25 docid14493 rev 8 figure 13. so-16 narrow footprint
docid14493 rev 8 23/25 L6390 order codes 25 11 order codes table 12. order codes order code package packaging L6390n dip-16 tube L6390d so-16 tube L6390dtr so-16 tape and reel
revision history L6390 24/25 docid14493 rev 8 12 revision history table 13. document revision history date revision changes 29-feb-2008 1 first release 09-jul-2008 2 updated: cover page, table 1 on page 4 , table 2 on page 5 , section 4 on page 6 , section 5 on page 8 , section on page 18 17-sep-2008 3 updated test condition values on table 7 and table 8 17-feb-2009 4 updated table 6 on page 8 , table 7 on page 10 , table 8 on page 12 added table 3 on page 6 11-aug-2010 5 updated table 1 on page 1 , table 6 on page 8 , table 8 on page 12 , table 9 on page 12 10-jul-2012 6 table 6 changed test conditions of dt and mdt values. table 7 added minimum values to i qccu -i qcc -i qbou - i qbo. table 7 changed v bo_thon and v bo_thoff minimum and maximum values. table 8 and table 9 added footnote to the title of the tables. changed hvg values on page 17. updated so-16 narrow mechanical data. changed section 7 and added figure 7 and figure 8 . 25-jul-2012 7 content reworked in section 9: bootstrap driver to improve readability, no technical changes. 20-jun-2014 8 updated section : applications on page 1 (replaced by new applications). updated section : description on page 1 (replaced by new description). updated table 1: device summary (moved from page 1 to page 24, updated title to table 12: order codes ). updated section 4.1: absolute maximum ratings on page 6 (removed note below table 3: absolute maximum ratings ). updated table 7 on page 10 (updated i qbo max. value). updated section : c boot selection and charging on page 18 (updated values of ?e.g.: hvg?). updated section 10: package information on page 20 (updated titles, reversed order of figure 11 and table 10 , figure 12 and table 11 , updated headers of table 10 and ta ble 11 ). minor modifications throughout document.
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